The present invention relates to packaging of semiconductor devices in general and more specifically to a method of forming a stacked package.
In tandem with the sophistication of electronic devices, there is a demand for greater functionality in smaller packages. Stacked die and stacked package three-dimensional (3D) packages have been developed to meet this demand. Typically, stacked die packages are formed by stacking multiple chips on one another. The chips in a stacked die package may be electrically coupled by wire bonding connections or flip chip connections. Stacked packages, on the other hand, are formed by stacking multiple packages on each other, where each package contains a single chip.
However, the formation of stacked die packages presents a number of problems. For instance, when stacked packages having wire bonding connections are formed, usually the upper chip is preferred to be smaller than the lower chip by an amount necessary for the area required to make the wire bonding connections. Accordingly, the mounting area for each successive upper chip is preferred to be progressively smaller, thereby imposing a limit on the number of packages that can be stacked.
Further, stacked packages are usually not processed in array (MAP) format; stacked packages are generally processed using glob top encapsulation or center gate molding and stacked only after singulation. For this reason, a longer manufacturing cycle time is required for the formation of stacked packages. Other problems associated with the formation of stacked packages include difficulty in ascertaining whether a die is functioning properly prior to stacking and larger overall package thickness for the same number of die stack.
In view of the foregoing, a need exists for a method of forming a reliable stacked package with increased functionality at low cost. Accordingly, it is an object of the present invention to provide a method of fabricating a reliable, low cost, high functionality stacked package.